FT-8800R tech documentation
From Interlock Rochester Wiki
(Difference between revisions)
| Line 150: | Line 150: | ||
|+ Main Unit packet structure | |+ Main Unit packet structure | ||
! Octet !! 0 !! 1 !! 2 !! 3 !! 4 !! 5 !! 6 !! 7 !! 8 !! 9 !! 10 !! 11 !! 12 !! 13 !! 14 !! 15 | ! Octet !! 0 !! 1 !! 2 !! 3 !! 4 !! 5 !! 6 !! 7 !! 8 !! 9 !! 10 !! 11 !! 12 !! 13 !! 14 !! 15 | ||
| - | |||
|- | |- | ||
| - | | '''0''' || U? || APO || PM<sub>L</sub> || F<sub>L</sub>.0.DP || F<sub>L</sub>.0.A | + | | '''0''' || U? || APO || PM<sub>L</sub> || F<sub>L</sub>.0.DP || SM<sub>L</sub>.8 | |
| - | | FL<sub>L</sub>.0.B || SBO | + | | F<sub>L</sub>.0.A ||FL<sub>L</sub>.0.B || SBO |
| - | | F<sub>L</sub>.0.F | + | | F<sub>L</sub>.0.C || F<sub>L</sub>.0.D || F<sub>L</sub>.0.E || F<sub>L</sub>.0.F |
| - | + | | F<sub>L</sub>.0.G || PL<sub>L</sub> || F<sub>L</sub>.0.H || SBZ | |
|- | |- | ||
| '''2''' || F<sub>L</sub>.0.I || F<sub>L</sub>.0.J || SM<sub>L</sub>.7 || F<sub>L</sub>.0.K | | '''2''' || F<sub>L</sub>.0.I || F<sub>L</sub>.0.J || SM<sub>L</sub>.7 || F<sub>L</sub>.0.K | ||
Revision as of 20:59, 24 January 2011
Contents |
Links
Technical
Pinouts
| Pin | Name | Description |
|---|---|---|
| 1 | MOD | Buffered Modulation (AF) Input (~2.2kΩ source impedance) |
| 2 | POWERSW | Active-low (pulled through 1KΩ resistor) momentary power switch signal |
| 3 | 9V | 9VDC regulated supply voltage for Panel Unit |
| 4 | GND | Ground |
| 5 | RXD | Head unit Asynchronous serial (19.2 kbps 8N1) Receive |
| 6 | TXD | Head unit Asynchronous serial (19.2 kbps 8N1) Transmit |
| Pin | Name | Description |
|---|---|---|
| 1 | SW2 | Matrix keypad column input |
| 2 | SW1 | Matrix keypad row input |
| 3 | 9V | 9VDC regulated supply voltage |
| 4 | GND | Ground |
| 5 | MIC | Electret microphone audio input |
| 6 | PTT | Active-low push-to-talk switch |
Protocol
| Parameter (Unit) | Description | Value |
|---|---|---|
| Communication | Asynchronous communication | 19.2 kbps 8-N-1 (8 data bits, no parity, 1 stop bit) |
| Head unit update period (ms) | Time between start of panel unit
TX packet to start of next packet | TBD (on order of 20) |
| Main unit update period (ms) | Time between start of main unit
TX packet to start of next packet | TBD (on order of 40) |
| Watchdog Time (s) | Minimum time between last update packet
from panel unit and when main unit shutdowns (powers off) | TBD |
TODO: Information for encoder dial button signal and WIRES (DXKEY) is missing.
| Octet | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
|---|---|---|---|---|---|---|---|---|
| 0 | Left encoder count since update
(2's complement - CW is positive) | SBO | ||||||
| 1 | Right encoder count since update
(2's complement - CW is positive) | SBZ | ||||||
| 2 | PTT input ADC
| SBZ | ||||||
| 3 | Right squelch ring ADC (7Fh: open squelch) | SBZ | ||||||
| 4 | Right volume control ADC (7Fh: max volume) | SBZ | ||||||
| 5 | SW1 keypad matrix row ADC
| SBZ | ||||||
| 6 | Left squelch ring ADC (7Fh: open squelch) | SBZ | ||||||
| 7 | Left volume control ADC (7Fh: max volume) | SBZ | ||||||
| 8 | SW2 keypad matrix column ADC
| SBZ | ||||||
| 9 | Panel right-side (multiplexed) buttons
| SBZ | ||||||
| 10 | Panel left-side (multiplexed) buttons
| SBZ | ||||||
| 11 | SET key | SBZ | ||||||
| 12 | Hyper-memory key
| |||||||
| Octet | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | U? | APO | PML | FL.0.DP | FL.0.A | FLL.0.B | SBO | FL.0.C | FL.0.D | FL.0.E | FL.0.F | FL.0.G | PLL | FL.0.H | SBZ | |
| 2 | FL.0.I | FL.0.J | SML.7 | FL.0.K | FL.0.L | FL.0.M | SML.6 | SBZ |
